This invention relates generally to frequency synthesizers and more particularly to a fractional-N frequency synthesizer employing more than one accumulator in a latched configuration, such that data need not "ripple" through more than one accumulator. The latched configuration operates synchronously and enables the system to operate at higher frequencies thereby reducing spurious signals. Reference is made to copending U.S. patent application Ser. Nos. 516,993, "Multiaccumulator Sigma-Delta Fractional-N Synthesis", filed in behalf of Hietala et al., on Apr. 30, 1990 and 516,897, "Fractional N/M Synthesis", filed in behalf of Black et al. on Apr. 30, 1990, each assigned to the assignee of the present invention. Reference is also made to U.S. patent application Ser. No. 576,333, "Latched Accumulator Fractional-N Synthesis with Residual Error Reduction", filed on the same date herewith in behalf of Hietala et al.
Phase-locked loop (PLL) frequency synthesis is a well known technique for generating one of many related signals from a voltage controlled oscillator (VCO). In a single loop PLL, an output signal from the VCO is coupled to a programmable frequency divider which divides by a selected integer number to provide a frequency divided signal to a phase detector which compares the frequency divided signal to a reference signal from another fixed frequency oscillator which, often, is selected for stability of frequency over time and environmental changes. Any difference in phase between the frequency divided signal and the reference signal is output from the phase detector, coupled through a loop filter, and applied to the VCO in a manner which causes the output signal from the VCO to change in frequency such that the phase error between the frequency divided signal and the reference signal is minimized. Since the programmable divider divides by integers only, the output frequency step size is constrained to be equal to the reference signal frequency. With the single loop PLL, an engineering compromise must be struck between the competing requirements of loop lock time, output frequency step size, noise performance, and spurious signal generation.
In order to overcome the limitations of the single loop PLL, programmable frequency dividers capable of dividing by non-integers have been developed. Output frequency step sizes which are fractions of the reference signal frequency are obtained while maintaining a high reference frequency and wide loop bandwidth. A discussion of fractional-N synthesis may be found in U.S. Pat. No. 4,816,774. As described therein, two accumulators are employed to simulate the performance of fractional synthesis of the switching between different integer values of divisors without the attendant spurious signals generated by such switching. The two accumulator technique acts to reduce the unwanted spurious signals by cancellation and loop filter rejection.
The reference signal frequency for the fractional-N frequency synthesizer is, therefore, determined by the step size of the VCO output frequency multiplied by the denominator of the programmable divider divisor. Fractional-N synthesis allows the use of a reference frequency which is much higher than the actual channel spacing and allows designs to use wider bandwidths due to the reduction of low frequency spurious outputs. Wider bandwidths allow fast lock times and the possibility of wideband modulation applied to the reference input or the fractional division scheme.
Unfortunately, the system is not perfect and generates some spurious signals output at a frequency equal to the channel spacing. The desired signal output purity is better than the no-fractional system, but by itself may still be insufficient for some high quality systems.
In order to minimize the effects of this spurious output, two accumulator fractional-N synthesis systems have been developed which spread out the spurious signals to frequencies at which filtering is inexpensive and simple. By using systems with more than two accumulators this benefit can be dramatically increased.
The present multiple accumulator systems all have a drawback in that the accumulator "ripple" the data. In other words, on every clock pulse the data must act on the entire digital network structure. This results in a relatively low upper frequency limit of operation for a multiple accumulator system due to propagation delays in the digital circuitry used to build the system.
The basic structure of a one-accumulator fractional N system is shown in the block diagram of FIG. 1. A VCO 101 generates an output signal which, typically is coupled to a programmable frequency divider 103 which has an output to a phase detector (.phi.) 105. The control input is a summation of a coarse channel setting and the output of the digital network which provides the fractional part of the division. The phase detector 105 conventionally compares the phase of the divided frequency, f.sub.v, to the phase of the reference signal frequency f.sub.r output from a reference oscillator 107 to produce a signal which is applied to a loop filter 109 and subsequently to the VCO 101 to phase-lock the VCO output signal.
The selection of the divisor value of variable frequency divider 103 is made by digital network 111 which, in previously known implementations such as described in Z-transform equivalent in U.S. Pat. No. 4,758,802, comprises a conventional adder 113, a comparator 115 (which produces a "carry out" signal when the input to the comparator 115 exceeds a given numerical value), and feedback logic 117 which substracts the denominator (if a carry output occurs) from the digital number representation output from adder 113 and comparator 115 before applying the digital number representation to the adder 113. A second digital number representation, which in a fractional-N synthesizer is the digital equivalent of the first differential of the offset phase with respect to time (the offset frequency), is applied to another input of the digital network 111. The overall effect of the digital network 111 is to integrate the differential phase and to apply to the PLL a control signal (in the form of a carry-out digital signal) which is a first order equivalent of the phase offset. The adder 113 sums the previous contents of the adder 113 with a d.phi./dt (a numerator) on each occurrence of the reference frequency signal f.sub.r. As described in U.S. Pat. No. 4,816,774, the adder 113 output is compared to a number (a denominator of a desired fractional part of the divisor when the divisor of frequency divider 103 is expressed as a sum of a whole number and a ##EQU1## If the contents of adder 113 exceed the denominator then the carry output is set true and the contents of the adder is reduced by the denominator in feedback logic 117 before the next reference pulse occurs.
As an example, assume the denominator is 13 and the numerator is 1. On every thirteenth reference pulse the adder 113 exceeds the denominator and generates a carry output which will increase the divisor of the frequency divider 103 by one for one reference signal, f.sub.r, pulse. This removes one pulse from the VCO 101 output signal and thus reduces the accumulated phase error by 360 degrees. This corresponds to a 1/13 division added to the nominal loop division number.
Shown in the Z-transform diagram of FIG. 2, is a Z-transform equivalent digital network 111' of this one accumulator system consistent with that disclosed in U.S. Pat. No. 4,758,802. The Z-transform equation for the single accumulator system is: ##EQU2## The Z-transform adder 201 is fed from the numerator (minus the denominator if an overflow occurs) and the previous adder contents represented by a z.sup.-1 (delay) block 203, 205. The comparison is considered to be a digital slicer with quantization error Q added at 207. The output from adder 207 is the digital number fed back to adder 201 and the carry out signal is taken as the output signal. For Z-transform analysis, however, no difference need be made between the output and the feedback signals.
At point B an equation can be written as follows. EQU B(z)=B(z)z.sup.-1 +A(z) or B(z)=A(z)/(1-z.sup.-1)
But EQU Data out=B(z)+Q and A(z)=Data in-B(z)-Q
Substituting this in and solving for B(z) then: EQU B(z)=Data in/(2-z.sup.-1)-Q/(2-z.sup.-1)
And solving for Data out: EQU Data out=Data in/(2-z.sup.-1)+Q(1-z.sup.-1)/(2-z.sup.-1)
This equation may now be converted to the frequency domain (Note that "v" is frequency normalized to the folding frequency: ##EQU3##
Thus, the data into into adder 201 is slightly low pass filtered and the quantization noise introduced by the digital network 111' is high pass filtered. The high pass filtering of the quantization noise has the effect of reducing the spurious signals occurring at the frequency of the channel to channel frequency spacing of the transceiver if the spurious occurs at a frequency much below the corner of the high pass. By selecting a PLL response with a low pass corner frequency much lower in frequency than the high pass corner it is possible to reject almost all the noise. In a single accumulator system, the high pass roll-off is 20 dB/decade. Thus the reference frequency must be large to push the high pass corner to large frequencies if sufficient noise suppression is to be obtained. (Or the PLL low pass must be very low in frequency and thus lose the benefit of wide bandwidth.)
To improve the high pass filtering of the basic fractional-N structure, it has been known to use fractional-N synthesis for systems using more than one accumulator. A two accumulator fractional-N synthesizer is disclosed in U.S. Pat. No. 4,204,174. Also, an example of a multiaccumulator fractional-N synthesizer is shown in the block diagram of FIG. 3, where the single digital network 111 of FIG. 1 is augmented by additional accumulators, in this instance, accumulator 303, accumulator 305, and accumulator 307.
In a multiaccumulator system, the contents of the first accumulator 111 becomes the Data input to the second accumulator 303. The contents of the second accumulator 303 becomes the data input to the third accumulator 305. Once the data is set at the output of adder 113 of accumulator 111, it must be transferred to the data input of adder 113 of accumulator 303. Once the data is set at the output of adder 113 of accumulator 303, it must be transferred to the data input of accumulator 305, etc. All of the transfer must be accomplished in one clock pulse (which is typically derived from the output of frequency divider 103). This process has been termed a "ripple" process, and the accumulators are known as "ripple" accumulators. Obviously, an upper limit on the speed and/or the number of accumulators is imposed by the ripple process.
The second accumulator 303 has its own Z-transform quantization error, Q2, in addition to the error of, Q1, the first accumulator. However both of these errors will be greatly reduced from the single accumulator case. The carry-output from the second accumulator 303 is applied to a delay logic element 309 and, after the differentiation produced by delay element 309, is applied to adder 311. The carry output from the comparator of accumulator 305 is twice differentiated by delay logic elements 313 and 315 and input to adder 311. The carry output from the comparator of accumulator 307 is thrice differentiated by delay logic elements 317, 319, and 321 and input to adder 311. The carry outputs, differentiated as described are added and output as an effective carry-out signal to be applied to frequency divider 103. Thus, the effect produced by the multiple accumulator system is to add the first order phase offset of the carry-output of accumulator 111 and the second order phase offset of the differentiated carry-output of accumulator 303, the third order phase offset of the twice diffentiated carry output of accumulator 305, and the fourth order phase offset of the thrice differentiated carry output of accumulator 307 for the effective carry-out signal.
For simplicity, the Z-transform model of the first and second accumulators is shwon in the diagram of FIG. 4. DO1 is the Data out of the first accumulator. From the above calculation: ##EQU4##
Di2 is the accumulator contents of the first accumulator: ##EQU5##
A similar equation to that above for DO2 is: ##EQU6##
Substitution in the expression for Di2 and then substituting in for DO1: ##EQU7## EQU But:DO3=DO2 (1-z.sup.-1) and Data out=DO1+DO3
Thus after some algebra: ##EQU8##
This representation is then converted to the frequency domain (Once again "v" is the frequency normalized to the folding frequency): ##EQU9##
In this case the high pass corner occurs at about the same frequency as in the one accumulator case but the frequency response of the high pass characteristic to the quantization noise is 40 db/decade. This allows the PLL to have a wider bandwidth, i.e., allows the fractional system to operate at a lower frequency, than in the one accumulator case while still maintaining the desired noise suppression.
The number of accumulators can theoretically be increased to any desired order. The resulting slope of the response of the high pass characteristic to the quantization noise will be the number of accumulators times 20 db/decade. The accumulators are "recombined" in what is known as a "Pascal's triangle method" as disclosed in U.S. Pat. No. 4,609,881. In general the higher order accumulators are recombined as (1-Z.sup.-1).sup.(n-1).
The aforementioned systems require that the data must ripple through all of the accumulators upon a clock pulse. For a higher order system this requirement limits the maximum accumulator clock rate and thus limits the noise suppression which can be obtained. The reason for this limit is that the propagation delay of each accumulator will add until the data cannot ripple through the system in one clock pulse period.